Title :
A low-power analog-to-digital converter for multi-gigabit wireless receiver in 90nm CMOS
Author :
Chuang, Kevin ; Yeh, David ; Pinel, Stephane ; Laskar, Joy
Author_Institution :
Georgia Electron. Design Center, Georgia Inst. of Technol., Atlanta, GA, USA
Abstract :
This paper presents a very low-power (3mW, 3.9mW) and high-speed (3GS/s, 5GS/s) flash ADC in a deep sub-micron CMOS technology. To save power and area, unnecessary building blocks of ADC are excluded. Optimization of comparator has been fully analyzed to reduce random offsets due to process scaling. Fabricated in 90nm CMOS, the experimental results demonstrate that the ADC occupying 0.0108mm2 active area achieves an effective resolution bandwidth (ERBW) of 1.25GHz and figure-of-merit (FOM) of 0.35pJ/conversion-step. The peak differential non-linearity (DNL) and integral non-linearity (INL) are 0.4LSB. The results obtained in this work is used to satisfy the stringent power requirement of a wireless mixed-signal receiver, specifically suitable for multi-gigabit amplitude shift keying (ASK) and binary phase shift keying (BPSK) demodulations.
Keywords :
CMOS integrated circuits; amplitude shift keying; analogue-digital conversion; comparators (circuits); low-power electronics; mixed analogue-digital integrated circuits; phase shift keying; radio receivers; CMOS technology; binary phase shift keying demodulation; comparator optimization; differential nonlinearity; effective resolution bandwidth; figure-of-merit; integral nonlinearity; low-power analog-to-digital converter; multigigabit amplitude shift keying; multigigabit wireless receiver; wireless mixed-signal receiver; CMOS integrated circuits; CMOS technology; Converters; Frequency measurement; Optimization; Solid state circuits; Wireless communication;
Conference_Titel :
Microwave Integrated Circuits Conference (EuMIC), 2010 European
Conference_Location :
Paris
Print_ISBN :
978-1-4244-7231-4
