• DocumentCode
    530919
  • Title

    Distributed modeling of layout parasitics effects in CMOS power devices

  • Author

    Chan, Doris A. ; Feng, Milton

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Univ. of Illinois at Urb ana-Champaign, Urbana, IL, USA
  • fYear
    2010
  • fDate
    27-28 Sept. 2010
  • Firstpage
    242
  • Lastpage
    245
  • Abstract
    The effects of distributed power device model optimization and extraction techniques are incorporated to predict the fT, fmax, transducer power gain and output power in 130 nm CMOS. Small signal and large signal of BSEVI-RF model, ICF-D1 model, and measured power device results are compared for model verification.
  • Keywords
    CMOS integrated circuits; MMIC power amplifiers; field effect MMIC; integrated circuit layout; power MOSFET; power integrated circuits; semiconductor device models; transducers; BSEVI-RF model; CMOS power devices; ICF-D1 model; distributed power device model optimization; extraction techniques; layout parasitics effects; output power; size 130 nm; transducer power gain; Capacitance; Integrated circuit modeling; Logic gates; MOSFETs; Power measurement; Predictive models; Semiconductor device modeling;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Microwave Integrated Circuits Conference (EuMIC), 2010 European
  • Conference_Location
    Paris
  • Print_ISBN
    978-1-4244-7231-4
  • Type

    conf

  • Filename
    5613699
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=530919