Physical analysis of substrate noise coupling in mixed circuits in SoC technology

The paper presents physics based approach for modelling of substrate noise coupling in mixed integrating circuit ICs. It shows that substrate noise corresponds a spontaneous movements of free carriers generated in the Nwell and Pwell region of digitals circuits. The transit time of these carriers from Nwell and Pwell region to silicon substrate introduces a high cutoff frequency controlled by the layers geometric dimensions and the doping profile. This frequency depends on the switching characteristics of digitals circuits. We have shown that the power level at this frequency is higher than the power at the clock and its harmonics, hence it´s the major contributor to substrate noise. The analysis and the results were performed on the DEVEDIT3D, ATLAS and MIXEDMODE tools from SIL VACO.