Title :
A 3 bit 20 GS/s flash ADC in 65 nm low power CMOS technology
Author :
Ferenci, Damir ; Grözing, Markus ; Lang, Felix ; Berroth, Manfred
Author_Institution :
Inst. of Electr. & Opt. Commun. Eng., Univ. of Stuttgart, Stuttgart, Germany
Abstract :
A 20 GS/s 3 bit flash ADC with a wide analog bandwidth is realized in a 65 nm CMOS technology. By employing a fourfold parallelization a high sampling rate is achieved, while a large input bandwidth is maintained. The measured effective resolution is between 2 bit and 2.5 bit at a sampling rate of 12.8 GS/s and between 2 bit and 2.3 bit at a sampling rate of 18 GS/s. The power consumption of the ADC core is 2 W, the core area is 0.16 mm2.
Keywords :
CMOS analogue integrated circuits; analogue-digital conversion; low-power electronics; power consumption; ADC core; flash ADC; fourfold parallelization; high sampling rate; low power CMOS technology; power 2 W; power consumption; size 65 nm; wide analog bandwidth; CMOS integrated circuits; Clocks; Driver circuits; Frequency measurement; Signal resolution; Synchronization; Transmission line measurements;
Conference_Titel :
Microwave Integrated Circuits Conference (EuMIC), 2010 European
Conference_Location :
Paris
Print_ISBN :
978-1-4244-7231-4
