A low-noise 8–12 GHz fractional-N PLL in SiGe BiCMOS technology

Author

Follmann, Rüdiger ; Köther, Dietmar ; Herzel, Frank ; Winkler, Frank ; Heyer, Heinz-Volker

Author_Institution

IMST GmbH, Kamp-Lintfort, Germany

fYear

2010

fDate

27-28 Sept. 2010

Firstpage

98

Lastpage

101

Abstract

A single-chip low-noise fractional-N PLL with 40 percent tuning range is presented. The design employs two integrated VCOs controlled by three digital and two analog signals. The synthesizer is based on a dual-loop configuration. It is tuneable from 8.1 GHz to 12.4 GHz and features an f/2 output. In integer mode phase noise is below -100 dBc/Hz at all frequency offsets larger than 10 kHz. In fractional mode the phase noise is below -90 dBc/Hz in loop. In integer mode the RMS phase error is as low as 0.53 degree.

Keywords

BiCMOS integrated circuits; frequency synthesizers; mean square error methods; phase locked loops; phase noise; silicon compounds; voltage-controlled oscillators; BiCMOS technology; RMS phase error; analog signal; digital signal; dual-loop configuration; fractional mode; frequency 8 GHz to 12 GHz; frequency 8.1 GHz to 12.4 GHz; frequency offsets; integer mode; integrated VCO; phase noise; single-chip low-noise fractional-N PLL; synthesizer; tuning range; BiCMOS integrated circuits; Phase locked loops; Phase noise; Silicon germanium; Synthesizers; Tuning; Voltage-controlled oscillators;

fLanguage

English

Publisher

ieee

Conference_Titel

Microwave Integrated Circuits Conference (EuMIC), 2010 European

Conference_Location

Paris

Print_ISBN

978-1-4244-7231-4

Type

conf

Filename

5613771