DocumentCode
531560
Title
A PLL with ultra low phase noise for millimeter wave applications
Author
Gai, Xiaolei ; Liu, Gang ; Chartier, Sébastien ; Trasser, Andreas ; Schumacher, Hermann
Author_Institution
Inst. of Electron Device & Circuits, Univ. of Ulm, Ulm, Germany
fYear
2010
fDate
28-30 Sept. 2010
Firstpage
69
Lastpage
72
Abstract
An ultra low noise phase locked loop (PLL) for millimeter wave applications is presented. The complete design includes a mixer type phase detector, a divide-by-32 frequency divider, a VCO and an off-chip active low pass filter. A method for the phase noise optimization of the PLL is described. The chip was designed using a 0.8 μm SiGe HBT technology. The frequency can be tuned from 29.9 GHz to 33.1 GHz. The output phase noise is around -112 dBc/Hz at 1 MHz offset.
Keywords
frequency dividers; heterojunction bipolar transistors; low-pass filters; millimetre wave detectors; optimisation; phase detectors; phase locked loops; phase noise; HBT technology; PLL; VCO; frequency divider; millimeter wave applications; mixer type phase detector; off-chip active low pass filter; output phase noise; phase noise optimization; ultra low noise phase locked loop; ultra low phase noise;
fLanguage
English
Publisher
ieee
Conference_Titel
Microwave Conference (EuMC), 2010 European
Conference_Location
Paris
Print_ISBN
978-1-4244-7232-1
Type
conf
Filename
5616469
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