Study on integral-limits for estimating high-stability-clock´s jitter

Power-law-integral is one normal conversion formula to indirectly estimate sub-picosecond-level clock jitter, but its result depended by the integral-upper-limit and lower-limit. How to choose integral limits are the key problem to use this formula for more reasonable. This paper introduces clock jitter in time domain and frequency domain, clock´s phase noise characteristics, and from phase noise into jitter formula. Analysis the relationship between power-law integral lower limit and clock signal frequency, A/D conversion resolution, etc., proposed a formula to estimate the limit. To upper limit, comparative analysis of the quantization noise power spectral density and clock signal´s phase noise power spectral density, the choosing up-limit reference principle.