Title :
Overview of inter-communication mechanism on multi-core processor
Author :
Xingang Ju ; Qin, Yi ; Yang, Liang ; Huang, Shitan
Author_Institution :
Xi´´an Microelectron. Technol. Inst., Xi´´an, China
Abstract :
As the increasing in chip density, on-chip communication will be a key factor in determining the performance and power consumption of the multi-core processor. Some typical communication mechanisms of the multi-core processor at present are introduced in detail in this paper, such as cache-shared bus structure, shared-bus structure and NoC-based structure, and there advantages, disadvantages and ranges of application are also analyzed. Finally, the basic architecture and research of the NoC are presented in particularly, and its advantages are also analyzed, such as scalability, reusability and predictability. NoC is inevitable choice to meet the high level of integration chips.
Keywords :
cache storage; microprocessor chips; network-on-chip; power consumption; system buses; NoC-based structure; cache-shared bus structure; chip density; intercommunication mechanism; multicore processor; on-chip communication; power consumption; Communication networks; Process control; System-on-a-chip; Interconnect technology; Multi-core processor; NoC; On-chip communication;
Conference_Titel :
Computer Application and System Modeling (ICCASM), 2010 International Conference on
Conference_Location :
Taiyuan
Print_ISBN :
978-1-4244-7235-2
Electronic_ISBN :
978-1-4244-7237-6
DOI :
10.1109/ICCASM.2010.5620488
