• DocumentCode
    53262
  • Title

    InAs Planar Nanowire Gate-All-Around MOSFETs on GaAs Substrates by Selective Lateral Epitaxy

  • Author

    Chen Zhang ; Wonsik Choi ; Mohseni, Parsian K. ; Xiuling Li

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Univ. of Illinois, Urbana, IL, USA
  • Volume
    36
  • Issue
    7
  • fYear
    2015
  • fDate
    Jul-15
  • Firstpage
    663
  • Lastpage
    665
  • Abstract
    High indium content III-V materials are one of the most promising candidates for beyond Si CMOS technologies. We present InAs planar nanowire (NW) MOSFETs grown directly on a semi-insulating GaAs (100) substrate by the selective lateral epitaxy (SLE) method via the metal-seeded planar vapor-liquid-solid mechanism. Despite a ~7% lattice mismatch, in-plane and self-aligned single-crystal InAs NWs are grown epitaxially on GaAs. Such heterogeneous SLE provides a potential solution for the integration of different channel materials on one substrate. Gate-all-around MOSFET devices are fabricated by releasing the NW channel from the substrate through a combination of digital etching and selective etching processes. The device with a NW width of 30 nm and gate length of 350 nm shows an ION/IOFF ratio of 104 and a peak transconductance of 220 mS/mm at Vds = 0.5 V.
  • Keywords
    III-V semiconductors; MOSFET; etching; gallium arsenide; indium compounds; nanowires; GaAs; InAs; SLE method; channel material integration; digital etching process; heterogeneous SLE; high-indium content III-V materials; in-plane-self-aligned single-crystal indium arsenide NW; indium arsenide NW MOSFET; lattice mismatch; metal-seeded planar vapor-liquid-solid mechanism; planar nanowire gate-all-around MOSFET; selective etching process; selective lateral epitaxy method; semiinsulating gallium arsenide substrate; silicon CMOS technologies; size 30 nm; size 350 nm; voltage 0.5 V; Epitaxial growth; Etching; Gallium arsenide; Gold; Logic gates; MOSFET; Substrates; III-V MOSFETs; III???V MOSFETs; InAs; Nanowire; Selective Lateral Epitaxy; VLS Growth; VLS growth; nanowire; selective lateral epitaxy;
  • fLanguage
    English
  • Journal_Title
    Electron Device Letters, IEEE
  • Publisher
    ieee
  • ISSN
    0741-3106
  • Type

    jour

  • DOI
    10.1109/LED.2015.2429680
  • Filename
    7101804