DocumentCode :
532976
Title :
Design and optimization of video compression system based on MPEG-4
Author :
Jiang, Chunlei ; Zhu, Lan
Author_Institution :
Electr. & Inf. Eng. Coll., Northeast Pet. Univ., Daqing, China
Volume :
15
fYear :
2010
fDate :
22-24 Oct. 2010
Abstract :
This paper introduces a new method of video-compress based on MPEG-4. The coding algorithm adopts 3-D wavelet transformation and Shape Coding. In hardware implement, DSP chips and FPGA chips is adopted, FPGA completes the task of multiply clock periods operate, while DSP chips accomplishes the function of both the single clock period operate and the control of FPGA relocated calculation. Experimental result indicates the design can improve coding efficiency and get a good tradeoff between bit-rate and distortion. The method is shown to be simple, efficient and suitable for hardware implementation.
Keywords :
data compression; digital signal processing chips; field programmable gate arrays; optimisation; video coding; wavelet transforms; 3D wavelet transformation; DSP chips; FPGA chips; MPEG-4; multiply clock periods; shape coding; single clock period; video compression system design; video compression system optimization; Digital signal processing; Discrete wavelet transforms; Field programmable gate arrays; Silicon; DSP; DWT; FPGA; MPEG-4; Video Compression;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Computer Application and System Modeling (ICCASM), 2010 International Conference on
Conference_Location :
Taiyuan
Print_ISBN :
978-1-4244-7235-2
Electronic_ISBN :
978-1-4244-7237-6
Type :
conf
DOI :
10.1109/ICCASM.2010.5622621
Filename :
5622621
Link To Document :
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