DocumentCode
533360
Title
Engineering fully silicided large MOSFET driver for maximum It1 performance
Author
Iyer, Natarajan Mahadeva ; Hao, Jiang ; Kiong, Yap Hin ; Wei, Zhang Guo ; Wang, Xiaoping ; Chao, Cheng ; Verma, Purakh Raj
Author_Institution
GLOBALFOUNDRIES Singapore Pte. Ltd., Singapore, Singapore
fYear
2010
fDate
3-8 Oct. 2010
Firstpage
1
Lastpage
6
Abstract
Simultaneous optimization of LDD and Anti-punch-through implant conditions for ESD performance of very large width silicided output driver nMOSFET without snapback mode of operation is reported. Physical mechanisms responsible for performance improvement and device sensitivity to pulse rise time, with little or no dependence on TLP pulse width are detailed.
Keywords
MOSFET; circuit optimisation; driver circuits; electrostatic discharge; silicon compounds; transmission lines; ESD performance; LDD simultaneous optimization; SiO2; TLP pulse; antipunch-through implant conditions; device sensitivity; full silicided large MOSFET driver engineering; lightly doped drain; snapback mode; Driver circuits; Earth Observing System; Electrostatic discharge; Implants; Logic gates; Optimization; Performance evaluation;
fLanguage
English
Publisher
ieee
Conference_Titel
Electrical Overstress/ Electrostatic Discharge Symposium (EOS/ESD), 2010 32nd
Conference_Location
Reno, NV
Print_ISBN
978-1-58537-182-2
Electronic_ISBN
978-1-58537-182-2
Type
conf
Filename
5623729
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