DocumentCode
533399
Title
A scalable Verilog-A modeling method for ESD protection devices
Author
Li, Weiying ; Tian, Yu ; Wei, Linpeng ; Gill, Chai ; Mao, Wei ; Wang, Chuanzheng
Author_Institution
Freescale Semicond. China, Beijing, China
fYear
2010
fDate
3-8 Oct. 2010
Firstpage
1
Lastpage
10
Abstract
A novel and practical modeling method is presented for ESD protection devices, using behavior language Verilog-A. This method is simulator-independent, easy-to-implement, and extendable to different types of ESD protection devices. The triggering voltage, holding voltage, and turn-on resistance of ESD devices are scalable with device dimensions so that the models are suitable for predictive ESD simulations. This method has been validated by the good silicon correlation between the models of Zener-triggered bipolar devices and NMOS devices and transmission line pulsing measurement. These models are suitable for circuit level ESD simulations without encountering convergence problems.
Keywords
MOSFET; bipolar transistors; circuit simulation; electrostatic discharge; hardware description languages; semiconductor device models; ESD protection devices; NMOS devices; Zener-triggered bipolar device model; behavior language Verilog-A; circuit level ESD simulations; holding voltage; scalable Verilog-A modeling method; simulator-independent method; transmission line pulsing measurement; triggering voltage; turn-on resistance; Clamps; Convergence; Electrostatic discharge; Fitting; Hardware design languages; Integrated circuit modeling; Mathematical model;
fLanguage
English
Publisher
ieee
Conference_Titel
Electrical Overstress/ Electrostatic Discharge Symposium (EOS/ESD), 2010 32nd
Conference_Location
Reno, NV
Print_ISBN
978-1-58537-182-2
Electronic_ISBN
978-1-58537-182-2
Type
conf
Filename
5623782
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