• DocumentCode
    533432
  • Title

    Fair multithreading on packet processors for scalable network virtualization

  • Author

    Wu, Qiang ; Shanbhag, Shashank ; Wolf, Tilman

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Univ. of Massachusetts, Amherst, MA, USA
  • fYear
    2010
  • fDate
    25-26 Oct. 2010
  • Firstpage
    1
  • Lastpage
    11
  • Abstract
    Network virtualization requires careful control of networking resources, including link bandwidth, router memory, and packet processing time. Isolation and fair sharing of processing resources in current high-performance packet processors occur at the granularity of entire processor cores. Scaling of network virtualization to larger numbers of parallel slices requires a more fine-grained processor sharing mechanism. Our work presents a novel approach, called Fair Multithreading (FMT), that allows hardware threads to share a processor core while ensuring isolation and weighted fair access. We present an analysis of the FMT algorithm and a prototype implementation on a NetFPGA system. Our evaluation results indicate that FMT can be implemented at speeds that are necessary to make scheduling decisions at the instruction level. We show the impact of having such fine-grained processor schedulers in substrate nodes by comparing the resource utilization of virtual network slices in our system to traditional whole-core allocations. Our simulation results show the FMT-based substrate networks can be utilized more efficiently and more virtual network requests can be accommodated. These results indicate the significant improvement in system scalability that can be gained from our fine-grained processor scheduling system.
  • Keywords
    local area networks; multi-threading; processor scheduling; resource allocation; NetFPGA system; fair multithreading; link bandwidth; network virtualization; packet processor; processor scheduling; processor sharing; router memory; virtual network; Hardware; Instruction sets; Multithreading; Operating systems; Processor scheduling; Resource management; Algorithms; Design; Performance;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Architectures for Networking and Communications Systems (ANCS), 2010 ACM/IEEE Symposium on
  • Conference_Location
    La Jolla, CA
  • Print_ISBN
    978-1-4244-9127-8
  • Electronic_ISBN
    978-1-4503-0379-8
  • Type

    conf

  • Filename
    5623849