Minimizing temperature sensitivity of dual-Vt CMOS circuits using Simulated-Annealing on ISING-like models

When considering modern ICs mapped onto nanometer CMOS technologies, increasingly higher power densities and larger power density spatial gradients are well known to be the main source of thermal hot-spots, which in turn may cause huge performance variations, low-energy efficiency, and thus, low reliability. The resulting difficulties in managing temperature have become one of the major challenges for circuit designers and EDA tools. In this work we present a gate-level thermal-aware low-power design technique, which aims at providing the circuit with temperature insensitivity (i.e., minimum timing variation under temperature fluctuations) while minimizing the active static power consumption. The proposed solution, based on a Simulated Annealing optimization algorithm applied on a ISING-like analytical model, exploits the Inverted Temperature Dependence (ITD) of nanometer CMOS gates. Under ITD, in fact, those gates that have low threshold voltages (LVT) show a delay which increases at higher temperature, while gates with high threshold voltage (HVT) show the opposite behavior, namely, they get faster as they get warmer. The right sequence of LVT and HVT cells may compensate the thermal effects on the critical paths, thus guaranteeing temperature insensitivity. Experimental results performed on a set of public benchmarks mapped onto an industrial 65nm technology show performance variations close to zero, with a significant leakage power reduction compared to standard single threshold voltage circuits.