Approach to 4-Core MPSoC Design Based on Matrix Computing

Author

Li Dongsheng ; Li Yilei ; Yong Aixia ; Gao Minglun

Author_Institution

Inst. of VLSI Design, Hefei Univ. of Technol., Hefei, China

fYear

2010

fDate

7-9 Nov. 2010

Firstpage

1

Lastpage

4

Abstract

The multi-core technique will play an important role in high density computing, therefore, it is significant to design MPSoC with handy intellectual property core. This paper gives the design of the 4-core multi-processor system on chip (MPSoC) based on hierarchy AHB bus architecture in RTL, and the testing results indicate that the speed increases along with the increasing dimension of the multiplication matrix. When the parallel program is beyond 95 percent in the total program, such as the 32 dimension matrix, the system speedup ratio is theoretically equal to the number of the cores integrated in MPSoC.

Keywords

logic design; multiprocessing systems; system-on-chip; 4-core MPSoC design; 4-core multiprocessor system on chip; AHB bus architecture; high density computing; intellectual property core; matrix computing; multicore technique; multiplication matrix; Multicore processing; Pipeline processing; Process control; Reduced instruction set computing; Testing; Timing;

fLanguage

English

Publisher

ieee

Conference_Titel

E-Product E-Service and E-Entertainment (ICEEE), 2010 International Conference on

Conference_Location

Henan

Print_ISBN

978-1-4244-7159-1

Type

conf

DOI

10.1109/ICEEE.2010.5661052

Filename

5661052