Analysis and Mapping of Video Decoding Algorithm on Coarse-Grain Reconfigurable Array

Because of the high computation demand for multimedia applications like video decoding, there is a need to develop flexible and high performance reconfigurable computing architectures. Taking video decoding algorithm as an example, we propose a reconfigurable computing realization solution of multimedia application. Based on the analysis of parallelism in video decoding algorithm, a hardware platform was chosen. Then the video decoding algorithm was adjusted according to the character of platform, and mapped onto the it. Electronic system level simulation of the mapping was made, and the result was compared to the result on arm. The result shows there is about 35% improvement by speed in DCT and about 145% in sample interpolation algorithm. In the last part of the paper, some improvement of the hardware platform was proposed according to the character of video decoding.