A Design of Network Digital Audio Public Address System

Author

Fu Yueqian ; Tan Biao

Author_Institution

Sch. of Electron. & Inf. Eng., Ningbo Univ. of Technol., Ningbo, China

fYear

2010

fDate

7-9 Nov. 2010

Firstpage

1

Lastpage

3

Abstract

This paper describes a method of digital audio public address (PA) system based on Ethernet. The main framework of the system is proposed and the core techniques are analyzed. The hardware design of network audio devices and software design are described in details in this paper. CYCLONE II EP2C5FA484 programmable FPGA chip and audio codec VS1003 are proposed in the network audio terminal design, in which μc/OS is performed as the kernel of Nios II processor. Combination of network switch and IEEE 1588 Clock Synchronization are proposed to achieve real-time audio signal transmission. The designed system has high performance and is cost effective.

Keywords

audio systems; field programmable gate arrays; hardware-software codesign; local area networks; synchronisation; CYCLONE II EP2C5FA484 programmable FPGA chip; IEEE 1588 Clock Synchronization; Nios II processor; audio codec VS1003; digital audio public address system; ethernet; hardware design; network audio devices; network switch; real-time audio signal transmission; software design; Ethernet networks; Field programmable gate arrays; Real time systems; Servers; Software; Switches; Synchronization;

fLanguage

English

Publisher

ieee

Conference_Titel

E-Product E-Service and E-Entertainment (ICEEE), 2010 International Conference on

Conference_Location

Henan

Print_ISBN

978-1-4244-7159-1

Type

conf

DOI

10.1109/ICEEE.2010.5661332

Filename

5661332