Title :
FPGA power and timing optimization: architecture, process, and CAD
Author :
Zhang, Chun ; Cheng, Lerong ; Wang, Lingli ; Tong, Jiarong
Author_Institution :
State Key Lab. of ASIC & Syst., Fudan Univ., Shanghai, China
Abstract :
Field programmable gate arrays (FPGAs) allow the same silicon implementation to be programmed or reprogrammed for a variety of applications. It provides low NRE (non-recurring engineering) cost and short time to market. As CMOS technology continue to scale down to nanometer, increased power consumption and worsened process variation become crucial constraints for FPGAs. The survey reviews the process and architecture evaluation and CAD algorithms to optimize power and delay for FPGAs.
Keywords :
CAD; CMOS integrated circuits; circuit optimisation; field programmable gate arrays; low-power electronics; CAD algorithms; CMOS technology; FPGA power; architecture evaluation; field programmable gate arrays; low NRE cost; nonrecurring engineering; power consumption; timing optimization; Delay; Design automation; Field programmable gate arrays; Logic gates; Routing; Strontium; Switches;
Conference_Titel :
Computational Problem-Solving (ICCP), 2010 International Conference on
Conference_Location :
Lijiang
Print_ISBN :
978-1-4244-8654-0
