Title :
TAT cost calculation of a wafer in a lot
Author :
Okumura, Hiroyuki
Author_Institution :
NEC Electronics Corporation, Sagamihara, Kanagawa, Japan
Abstract :
TAT cost standard is defined and proposed by a relation between lot size, TAT and wafer cost in this paper. How to treat large variations of waiting time in a site data is excogitated. Proposed TAT costs equations and corrections can be used in a short TAT rate charge, TAT management etc. of many lines and products.
Keywords :
Equations; Least squares approximation; Manufacturing; Materials; Mathematical model; Productivity;
Conference_Titel :
Semiconductor Manufacturing (ISSM), 2008 International Symposium on
Conference_Location :
Tokyo, Japan
Electronic_ISBN :
1523-553X
