Integrated defect sampling method by using design attribute for high sensitivity inspection in 45nm production environment

Higher inspection sensitivity may be necessary for capturing the smaller defects of interest (DOI) dictated by reduced minimum design features, especially when establishing a baseline defect Pareto during R&D and early ramp stages. In this paper, an advanced defect filtering and sampling approach is studied. By associating the GDS clip (design layout) information with every defect and extracting design attributes, the new integrated sampling methodology can separate systematic defects and categorize random defects, then use this information to improve random DOI sampling rates and DOI type coverage even on wafers having high defect counts.