• DocumentCode
    53967
  • Title

    A Step-Up Switched-Capacitor Multilevel Inverter With Self-Voltage Balancing

  • Author

    Yuanmao Ye ; Cheng, K.W.E. ; Junfeng Liu ; Kai Ding

  • Author_Institution
    Dept. of Electr. Eng., Hong Kong Polytech. Univ., Kowloon, China
  • Volume
    61
  • Issue
    12
  • fYear
    2014
  • fDate
    Dec. 2014
  • Firstpage
    6672
  • Lastpage
    6680
  • Abstract
    The objective of this paper is to propose a new inverter topology for a multilevel voltage output. This topology is designed based on a switched capacitor (SC) technique, and the number of output levels is determined by the number of SC cells. Only one dc voltage source is needed, and the problem of capacitor voltage balancing is avoided as well. This structure is not only very simple and easy to be extended to a higher level, but also its gate driver circuits are simplified because the number of active switches is reduced. The operational principle of this inverter and the targeted modulation strategies are presented, and power losses are investigated. Finally, the performance of the proposed multilevel inverter is evaluated with the experimental results of an 11-level prototype inverter.
  • Keywords
    PWM invertors; driver circuits; switched capacitor networks; capacitor voltage balancing; gate driver circuits; inverter topology; multilevel voltage output; power losses; self voltage balancing; step up switched capacitor multilevel inverter; switched capacitor technique; Capacitors; Driver circuits; Harmonic analysis; Inverters; Pulse width modulation; Topology; H-bridge; multilevel inverter; selective harmonic elimination (SHE); sinusoidal pulsewidth modulation (SPWM); switched capacitor (SC);
  • fLanguage
    English
  • Journal_Title
    Industrial Electronics, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0278-0046
  • Type

    jour

  • DOI
    10.1109/TIE.2014.2314052
  • Filename
    6779655