Title :
Implementation of digital HDTV video decoder by multiple multimedia video processors
Author :
Lee, C.L. ; Cheng S. Ho, Cheng S. Ho ; Shwu-Fang Tsai, Shwu-Fang Tsai ; Ching-Fu Wu, Ching-Fu Wu ; Jui-Ying Cheng, Jui-Ying Cheng ; Li-wei Wang ; Wang, Chingyue
Abstract :
A digital HDTV video decoder system is designed and implemented by using multiple multimedia video processors in a loosely coupled architecture. This decoder decompresses video bitstream up to 20 Mbits/s and produce analog output at HDTV pixel rate. This design has the advantages of low cost and small system size.
Keywords :
Computer architecture; Decoding; HDTV; Multimedia communication; Program processors; Streaming media; Transform coding;
Conference_Titel :
Consumer Electronics, 1996. Digest of Technical Papers., International Conference on
Print_ISBN :
0-7803-3029-3
DOI :
10.1109/ICCE.1996.517225
