Analysis of parasitic effects in ultra wideband low noise amplifier based on EM simulation

Author

Seong, Nackgyun ; Lee, Youngseong ; Jang, Yohan ; Choi, Jaehoon

Author_Institution

Dept. of Electron. & Comput. Eng., Hanyang Univ., Seoul, South Korea

fYear

2010

fDate

7-10 Dec. 2010

Firstpage

374

Lastpage

377

Abstract

Layout parasitic effects can significantly affect the performance of CMOS RF integrated circuits such as low noise amplifier (LNA), mixer and etc. Therefore, the analysis of parasitic effects of layout in CMOS process has become very important. In this paper, we studied a fast approach to predict the parasitic effects of an on-chip interconnect structure based on EM simulation. This approach is applied to analyze the parasitic effects in ultra wideband (UWB) LNA design. Numerical results reveal that the parasitic effects of interconnect is very critical to maintain the desired performance of a UWB LNA.

Keywords

CMOS analogue integrated circuits; low noise amplifiers; ultra wideband communication; CMOS RF integrated circuit; EM simulation; UWB LNA design; layout parasitic effects; on-chip interconnect structure; ultra wideband low noise amplifier; Analytical models; CMOS integrated circuits; CMOS technology; Numerical models; Radio frequency; Semiconductor device modeling; EM-based modeling approach; RF CMOS Integrated circuit; UWB LNA; layout interconnect effect;

fLanguage

English

Publisher

ieee

Conference_Titel

Microwave Conference Proceedings (APMC), 2010 Asia-Pacific

Conference_Location

Yokohama

Print_ISBN

978-1-4244-7590-2

Electronic_ISBN

978-1-902339-22-2

Type

conf

Filename

5728637