A novel digital background calibration technique for pipelined ADCs

This paper presents a novel and simple digital background calibration technique to eliminate the linear errors of 1.5bit/stage pipelined analog-to-digital converters (ADCs) caused by capacitor mismatch and finite DC gain of stage amplifiers. In this technique, by injecting a determined calibration signal in a modified conventional multiplying digital-to-analog converter (MDAC) and split structure, the errors are measured while it is not necessary to use an accurate calibration signal. As a case study, the technique is tested on a prototype 12bit 1.5bit/stage split pipelined ADC with 60 dB amplifier DC gain and 0.1% capacitor mismatch using MATLAB and Simulink environment simulations. After calibration, the ADC achieves 71 dB SNDR and 82dB SFDR which are restricted to 58dB and 63dB respectively before calibration.