DocumentCode :
54266
Title :
Four-Valued Reasoning and Cyclic Circuits
Author :
Gange, Graeme ; Horsfall, Benjamin ; Naish, Lee ; Sondergaard, Harald
Author_Institution :
Dept. of Comput. & Inf. Syst., Univ. of Melbourne, Melbourne, VIC, Australia
Volume :
33
Issue :
7
fYear :
2014
fDate :
Jul-14
Firstpage :
1003
Lastpage :
1016
Abstract :
Allowing cycles in a logic circuit can be advantageous, for example, by reducing the number of gates required to implement a given Boolean function, or a set of functions. However, a cyclic circuit may easily be ill behaved. For instance, it may have some output wire oscillation instead of reaching a steady state. Propositional three-valued logic has long been used in tests for good behavior of cyclic circuits; a symbolic evaluation method known as ternary analysis provides one criterion for good behavior under certain assumptions about wire and gate delay. We revisit ternary analysis and argue for the use of four truth values. The fourth truth value allows for the distinction of undefined and underspecified behavior. Ability to under specify behavior is useful, because, in a quest for smaller circuits, an implementor can capitalize on degrees of freedom offered in the specification. Moreover, a fourth truth value is attractive because, rather than complicating (ternary) circuit analysis, it introduces a pleasant symmetry, in the form of contra-duality, as well as providing a convenient framework for manipulating specifications. We use this symmetry to provide fixed point results that clarify how two-, three-, and four-valued analyses are related, and to explain some observations about ternary analysis.
Keywords :
Boolean functions; multivalued logic circuits; Boolean function; complicating circuit analysis; contra-duality; cyclic circuits; degrees of freedom; four-valued reasoning; fourth truth value; gate delay; logic circuit; output wire oscillation; pleasant symmetry; propositional three-valued logic; symbolic evaluation method; ternary analysis; Cognition; Delays; Integrated circuit modeling; Lattices; Logic gates; Upper bound; Wires; Boolean functions; circuit optimization; combinational circuits; multivalued logic;
fLanguage :
English
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
0278-0070
Type :
jour
DOI :
10.1109/TCAD.2014.2304176
Filename :
6835151
Link To Document :
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