Performance and resource optimization of NoC router architecture for master and slave IP cores

System-on-Chip architectures incorporate several IP cores with well defined master and slave characteristics in terms of on-chip communication. The paper presents a parameterized NoC router architecture that can be optimized for performance and resource requirement by exploiting the master or slave behavior of the cores that are attached to it. We implemented the proposed router architecture for the IBM Coreconnect protocol and mapped it on the Xilinx Virtex series FPGA. We compared the FPGA based implementation against industry strength bus design that supports the IBM Coreconnect protocol, namely processor local bus (PLB). For similar resource requirements, our design demonstrated a 97.6% increase in throughput and 76.53% decrease in latency in comparison to the PLB. We also compared the proposed architecture with an existing NoC router design that is oblivious to master/slave IP cores. In the case of a router with all shared slaves our design resulted in 65.9% reduction in resources, 548% increase in throughput and 84.7% reduction in latency.