DocumentCode
543919
Title
Predictable execution adaptivity through embedding dynamic reconfigurability into static MPSoC schedules
Author
Yang, Chengmo ; Orailoglu, Alex
Author_Institution
Comput. Sci. & Eng. Dept., Univ. of California, La Jolla, CA, USA
fYear
2007
fDate
Sept. 30 2007-Oct. 3 2007
Firstpage
15
Lastpage
20
Abstract
Advances in semiconductor technologies have placed MPSoCs center stage as a standard architecture for embedded applications of ever increasing complexity. Because of real-time constraints, applications are usually statically parallelized and scheduled onto the target MPSoC so as to obtain predictable worst-case performance. However, both technology scaling trends and resource competition among applications have led to variations in the availability of resources during execution, thus questioning the dynamic viability of the initial static schedules. To eliminate this problem, in this paper we propose to statically generate a compact schedule with predictable response to various resource availability constraints. Such schedules are generated by adhering to a novel band structure, capable of spawning dynamically a regular reassignment upon resource variations. Through incorporating several soft constraints into the original scheduling heuristic, the proposed technique can furthermore exploit the inherent timing slack between dependent tasks, thus retaining the spatial and temporal locality of the original schedule. The efficacy of the proposed technique is confirmed by incorporating it into a widely adopted list scheduling heuristic, and experimentally verifying it in the context of single processor deallocations.
Keywords
embedded systems; multiprocessing systems; processor scheduling; reconfigurable architectures; system-on-chip; dynamic reconfigurability; embedded application; predictable execution adaptivity; real-time constraint; semiconductor technology; single processor deallocation; soft constraint; static MPSoC scheduling; technology scaling; Availability; Body regions; Dynamic scheduling; Processor scheduling; Schedules; Timing; Adaptive execution; multiprocessor task scheduling; reconfiguration;
fLanguage
English
Publisher
ieee
Conference_Titel
Hardware/Software Codesign and System Synthesis (CODES+ISSS), 2007 5th IEEE/ACM/IFIP International Conference on
Conference_Location
Salzburg
Print_ISBN
978-1-5959-3824-4
Type
conf
Filename
5753832
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