Comparison of different MOS-triggered SCR structures for on-chip ESD protection

Author

Ma, Fei ; Han, Yan ; Song, Bo ; Dong, Shurong ; Miao, Meng

Author_Institution

Dept. ISEE, Zhejiang Univ., Hangzhou, China

Volume

3

fYear

2011

fDate

11-13 March 2011

Firstpage

331

Lastpage

335

Abstract

Three types of MOS-triggered SCR structures: Merged MOS-triggered SCR, compact MOS-triggered SCR and boundary-MOS-triggered SCR devices have been fabricated and compared in 0.13 μm CMOS process for on-chip ESD protection. TLP testing results show boundary-MOS-triggered SCR structures can achieve adjustable and lower switching voltage, smaller turn-on resistance, faster turn-on speed, the best ESD robustness and sufficient latch-up immunity compared with other MOS-triggered SCRs.

Keywords

CMOS integrated circuits; MOS-controlled thyristors; electrostatic discharge; semiconductor device testing; thyristors; trigger circuits; CMOS process; MOS-triggered SCR structures; TLP testing; latch-up immunity; low switching voltage; on-chip ESD protection; size 0.13 mum; CMOS process; Clamps; Electrostatic discharge; Layout; Logic gates; Thyristors; Voltage measurement; Electrostatic discharge(ESD); Silicon-controlled rectifier(SCR); Transmission line pulse(TLP);

fLanguage

English

Publisher

ieee

Conference_Titel

Computer Research and Development (ICCRD), 2011 3rd International Conference on

Conference_Location

Shanghai

Print_ISBN

978-1-61284-839-6

Type

conf

DOI

10.1109/ICCRD.2011.5764207

Filename

5764207