A 10.4 dBm IIP3, 21 GHz LNA for K-band receiver front-end

Author

Liu, Baohong ; Mao, Junfa

Author_Institution

Center for Microwave & RF Technol., Shanghai Jiao Tong Univ., Shanghai, China

fYear

2011

fDate

20-22 April 2011

Firstpage

1

Lastpage

4

Abstract

A fully integrated 21 GHz LNA with 10.4 dBm IIP3 is presented in this paper. The LNA is composed of 2 common-source stages and fabricated through standard 0.18 um CMOS technology. By optimizing the gate-bias voltage of NMOS and interstage matching resistance, the linearity is enhanced. Measurement results show that the LNA can get 13.1 dB voltage gain, 5.9 dB NF, less than -10 dB input return loss and 10.4 dBm IIP₃ while its power dissipation is 12 mW at 1 V supply voltage. Compared to those published papers, this LNA get the highest linearity at comparative power dissipation.

Keywords

CMOS integrated circuits; electric resistance; low noise amplifiers; microwave amplifiers; microwave receivers; CMOS technology; IIP3; K-band receiver front-end; LNA; NMOS; comparative power dissipation; frequency 21 GHz; gain 13.1 dB; gate-bias voltage; interstage matching resistance; linearity; noise figure 5.9 dB; power 12 mW; size 0.18 mum; voltage 1 V; CMOS integrated circuits; Gain; K-band; Linearity; Logic gates; Noise measurement; Resistance;

fLanguage

English

Publisher

ieee

Conference_Titel

Microwave Conference Proceedings (CJMW), 2011 China-Japan Joint

Conference_Location

Hangzhou

Print_ISBN

978-1-4577-0625-7

Electronic_ISBN

978-7-308-08555-7

Type

conf

Filename

5774019