Forward block characteristic of a novel anti-ESD RF SOI LIGBT with a buried P-type layer

A novel anti-ESD RF SOI LIGBT with buried P-type layer (BPL) was proposed for improvement of its forward block characteristic. The proposed anti-ESD BPL RF SOI LIGBT consists of an additional buried P-type layer inserted between buried oxide layer and N-drift region based on the conventional RF SOI LIGBT structure and a built-in self-ESD-protection structure introduced in P-well region. When the proposed Device is biased in forward block state, the junction across the interface between N-drift region and buried P-type layer is reverse biased, which bears the most part of the vertical forward voltage drop instead of thick BOX. It was proved by process and device simulations with Silvaco TCAD that the anti-ESD BPL RF SOI LIGBT is benefit not only to improve its breakdown voltage without increasing the length of drift region but also to thin the thickness of its buried oxide and alleviate the effect of self-heating.