Digital logic simulation with compressed BDDs

The complexity of today´s VLSI chip designs makes verification a necessary step before fabrication. As a result, gate-level logic simulation has become an integral component of the VLSI circuit design process which verifies the design and analyzes its behavior. Because of the continuous growth of the size and complexity of circuits, more efficient simulation methods are needed to keep the gate-level logic verification time acceptably small. In this paper a new algorithm for parallel logic simulation is proposed based on the Structurally Synthesized Multiple Input BDDs (SSMIBDD). SSMIBDDs allow significant model size reduction compared to the traditional gate-level approach, and higher speed of simulation. At the same time, the new model preserves structural information about the circuit, which is needed for processing of faults and analyzing timing issues and hazards in circuits.