A comparative study of spectral purity of afractional-N frequency synthesizer for WiMAX applications employing several dithering techniques

This paper presents a Fractional-N frequency synthesizer for WiMAX applications. Fractional-N phase-locked loop (PLL) architecture is selected for higher reference frequency, smaller division ratio, better frequency resolution, and the possibility of agile switching between the channels. Fractional-N synthesizer also alleviates PLL design constraints for phase noise and reference spur. Employing accumulator and linear feedback shift registers (LFSR) are the common techniques to provide the fractional division ratio. The generation of the fractional spurs is the main shortcoming due to utilizing these kinds of dithering circuits. A sigma-delta fractional-N frequency synthesizer (FS) improves the phase noise performance using a spur reduction method. Several kinds of sigma-delta structures are designed and verified via MATLAB/SIMULINK. Also the core of the synthesizer apart from the dithering circuits is simulated using ADS2009 in 0.13 umCMOS technology. The simulation results illustrate a phase margin higher than 60°, a phase noise lower than -120 dBc/Hz and a settling time nearly to 4 μsec. In order to reduce the power dissipation, TSPC logic is used to design a programmable frequency divider which consumes less than 1 mW in 2 GHz.