FPGA implementation of JPEG-LS compression algorithm for real time applications

Author

Daryanavard, H. ; Abbasi, O. ; Talebi, R.

fYear

2011

fDate

17-19 May 2011

Firstpage

1

Lastpage

4

Abstract

This paper presents some propositions to reduce consuming memory and increase operational frequency of hardware implementation of JPEG-LS algorithm for real time applications. By enhancement in the algorithm and using fast divider, memory has been reduced by 24%. Also, considering the proposed non-stalling pipeline architecture by using forwarding technique to avoid hazards, circuit frequency has increased to 155.2 MHz and any 512×512 pixel image can be compressed in less than 1700 us at these frequency and architecture. Compressor architecture was described by VerilogHDL and implemented on ALTERA Stratix II FPGA.

Keywords

data compression; field programmable gate arrays; hardware description languages; image coding; pipeline processing; real-time systems; ALTERA Stratix II FPGA; JPEG-LS compression algorithm; VerilogHDL; compressor architecture; fast divider; forwarding technique; hardware implementation; operational frequency; real time applications; Context; Equations; Hardware; Image coding; Mathematical model; Pipelines; Pixel; FPGA; Forwarding; JPEG-LS; Memory; Pipeline;

fLanguage

English

Publisher

ieee

Conference_Titel

Electrical Engineering (ICEE), 2011 19th Iranian Conference on

Conference_Location

Tehran

Print_ISBN

978-1-4577-0730-8

Electronic_ISBN

978-964-463-428-4

Type

conf

Filename

5955727