DocumentCode :
547881
Title :
A technique for NoC routing based on Extended Compact Genetic Optimization Algorithm
Author :
Emrani, Z. ; Mohammadi, Karim
fYear :
2011
fDate :
17-19 May 2011
Firstpage :
1
Lastpage :
1
Abstract :
Network-on-chip (NoC) has been proposed as a solution for the global communication challenges of System-on-chip (SoC) design in the nanoscale technologies. This method tries to develop an efficient routing algorithm for Network-on-Chip. The proposed routing methodology, based on the Extended Compact Genetic Algorithm Optimization, is applied on the 2D-Mesh NoC platform to balance the link load. Experimental results show that this routing algorithm can efficiently assign deadlock-free, minimal routing paths for traffic traces in a short period of time.
Keywords :
circuit optimisation; genetic algorithms; mesh generation; network routing; network-on-chip; 2D-mesh NoC platform; NoC routing; SoC design; deadlock-free minimal routing path; extended compact genetic optimization algorithm; link load balancing; network-on-chip routing algorithm; system-on-chip design; traffic routing; Extended Compact Genetic; Network-on-chip (NoC); routing algorithm;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electrical Engineering (ICEE), 2011 19th Iranian Conference on
Conference_Location :
Tehran
Print_ISBN :
978-1-4577-0730-8
Type :
conf
Filename :
5955771
Link To Document :
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