A 10-bit 250MS/s pipelined ADC with a merged S/H & 1st stage using an optimal opamp sharing technique

Summary from only given. This paper presents a very high-speed low-power 10-bit pipelined ADC in a 90nm CMOS technology. A modified opamp-sharing technique is proposed which enables merging the S/H and first stage with optimum power saving. The new technique saves power by changing the bias currents of the inputand output stages of the amplifier. Stage scaling and low power dynamic comparators are also utilized to reduce power consumption more effectively. Using this approach, a 10-bit 250MSample/s pipelined ADC has been designed in a 90nm CMOS technology. According to HSPICE simulation results, the ADC achieves a 54.5dB SNDR with a nyquist-rate, 1Vp-p, diff input signal while consuming only 29mW with a 1V supply voltage.