Design and FPGA implementation of non-data aided timing and carrier recovery techniques for EDR Bluetooth standard

The main design issues for Bluetooth transceivers are not only low cost and low power consumption, but also quality performance. Classical designs of the Bluetooth receiver utilize data-aided techniques to correct carrier frequency offsets and symbol timing errors. Such techniques offer low cost and reasonable performance. Non-data aided techniques offer an alternate higher-performance approach to correct the same problems, at the penalty of an increased hardware complexity and cost. The purpose of this paper is to investigate the trade off between cost and performance when a Bluetooth 2.0 (Enhanced Data Rate) transceiver is designed using non-data aided techniques for clock and timing recovery.