Balanced minimal latency RNS addition for moduli set {2n −1, 2n, 2n +1}

The classical RNS moduli set RNS_C = {2ⁿ -1, 2ⁿ, 2ⁿ +1} is widely used in digital signal/image processing and generally in computer arithmetic with residue number systems (RNS). This popularity is due to possibility of efficient binary to/from RNS conversions and existence of modulo-(2ⁿ ± 1) adder architectures that are quite competitive with ordinary modulo-2ⁿ adders. For example, there are modulo-(2ⁿ -1) and -2ⁿ parallel prefix adders with the minimal latency of (3 + 2[log n]) unit gate delay (UGD), while latencies of the fastest existing modulo-(2ⁿ + 1) adders are 1, 2 or 3 UGDs more, depending on the encoding of residues. In particular diminished-1 (D1) representation of residues, in one design, has led to the least latency of (4 + 2[log n]) UGDs. Given that RNS_C addition is undertaken in three parallel computation channels corresponding to the three moduli, it is desirable to device a (3 + 2[log n])-UGD modulo-(2ⁿ + 1) adder as well. Therefore, we are motivated to improve the performance of the aforementioned least-latency D1 design. To achieve this goal in this paper, we use some of the existing techniques for zero handling associated with D1 representation. Our UGD measures are supported by the synthesis results, except for less than 5% deviation due to reasonably expected interconnection and routing effects.