Device modeling and system simulation of nanophotonic on-chip networks for reliability, power and performance

The nanophotonic network promises improved communications between cores in many-core systems. This paper discusses a novel modeling and simulation methodology. This infrastructure can compare performance, power consumption and reliability of nanophotonic network designs. Phenomenologically determined transfer-matrix device models are employed to characterize network performance under realistic multi-threaded applications, optical power transmission across the full wavelength-division multiplexing spectrum, and network reliability as affected by fabrication-induced process variation and run-time system thermal effects. Five recently proposed networks are analyzed to better elucidate advantages and limitations.