Reliability analysis and improvement for multi-level non-volatile memories with soft information

Author

Chen, Shih-Liang ; Ke, Bo-Ru ; Chen, Jian-Nan ; Huang, Chih-Tsun

Author_Institution

Dept. of Comput. Sci., Nat. Tsing Hua Univ., Hsinchu, Taiwan

fYear

2011

fDate

5-9 June 2011

Firstpage

753

Lastpage

758

Abstract

This paper presents the systematic methodology of error correction scheme using low-density parity check (LDPC) codes to improve the reliability and endurance of multi-level cell (MLC) non-volatile memories. Using our realistic error model, the LDPC architecture with the scheme of non-uniform reference voltages (NURV) is proposed to trade off among error correction capability, area, and throughput, which can improve the bit-error-rate significantly.

Keywords

error correction; flash memories; parity check codes; reliability; LDPC architecture; NURV; bit-error-rate improvement; error correction scheme; low density parity check; multilevel cell; multilevel nonvolatile memory; nonuniform reference voltage; realistic error model; reliability analysis; soft information; Ash; Computer architecture; Decoding; Error correction codes; Hardware; Parity check codes; Reliability; Error correction; low-density parity-check (LDPC) codes; multi-level cell (MLC); non-volatile flash memory; reliability;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation Conference (DAC), 2011 48th ACM/EDAC/IEEE

Conference_Location

New York, NY

ISSN

0738-100x

Print_ISBN

978-1-4503-0636-2

Type

conf

Filename

5981869