DocumentCode
549541
Title
Threadmill: A post-silicon exerciser for multi-threaded processors
Author
Adir, Allon ; Golubev, Maxim ; Landa, Shimon ; Nahir, Amir ; Shurek, Gil ; Sokhin, Vitali ; Ziv, Avi
Author_Institution
IBM Res. - Haifa, Haifa, Israel
fYear
2011
fDate
5-9 June 2011
Firstpage
860
Lastpage
865
Abstract
Post-silicon validation poses unique challenges that bring-up tools must face, such as the lack of observability into the design, the typical instability of silicon bring-up platforms and the absence of supporting software (like an OS or debuggers). These challenges and the need to reach an optimal utilization of the expensive but very fast silicon platforms lead to unique design considerations - like the need to keep the tool simple and to perform most of its operation on platform without interaction with the environment. In this paper we describe a variety of novel techniques optimized for the unique characteristics of the silicon platform. These techniques are implemented in Threadmill - a bare-metal exerciser targeting multi-threaded processors. Threadmill was used in the verification of the POWER7 processor with encouraging results.
Keywords
formal verification; multi-threading; multiprocessing systems; POWER7 processor verification; bare-metal exerciser targeting multithreaded processors; postsilicon exerciser; postsilicon validation; threadmill; Computer bugs; Debugging; Generators; Instruction sets; Joints; Registers; Silicon; Functional Verification; Multi-Threading; Post-Silicon Validation; Stimuli Generation;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference (DAC), 2011 48th ACM/EDAC/IEEE
Conference_Location
New York, NY
ISSN
0738-100x
Print_ISBN
978-1-4503-0636-2
Type
conf
Filename
5981876
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