A closed-form expression for estimating minimum operating voltage (VDDmin) of CMOS logic gates

In this paper, a closed-form expression for estimating a minimum operating voltage (V_DDmin) of CMOS logic gates is proposed. V_DDmin is defined as the minimum supply voltage at which circuits can operate correctly. V_DDmin of combinational circuits can be written as a linear function of the square-root of logarithm of the number of logic gates and its slope is proportional to the standard deviation of the within-die variation in the threshold voltage difference between PMOS and NMOS transistors. The proposed expression is verified with Monte Carlo simulations using various gate chains. The verification reveals that V_DDmin of inverter chains can be estimated within 11% error. The expression is also verified with silicon measurements in a 65nm CMOS process.