Complexity and the challenges of securing SoCs

There is a growing need to secure cryptographic keys and other secrets on SoCs and other large ASICs. For designers, smaller geometries make it more difficult to predict the precise physical and analog properties of digital logic blocks. In addition, high mask costs make it difficult to tune designs and raise the consequences of failure. For example, side channel attacks such as differential cryptanalysis can easily and noninvasively extract secrets from unprotected SoCs. Vulnerabilities can be difficult to anticipate, since common design and verification tools do not necessarily provide clear visibility into how devices will fail when pushed outside of its normal operational conditions. The security challenges facing the semiconductor industry are also in part educational; while security training is common for software developers, relatively few hardware engineers have specialized security knowledge. Some of these challenges can be mitigated at the architectural level, for example by using cryptographic constructions that provide inherent side-channel resistance irrespective of a device´s underlying analog properties.