DocumentCode
549598
Title
A high-parallelism distributed scheduling mechanism for multi-core instruction-set simulation
Author
Wu, Meng-Huan ; Wang, Peng-Chih ; Fu, Cheng-Yang ; Tsay, Ren-Song
Author_Institution
Nat. Tsing Hua Univ., Hsinchu, Taiwan
fYear
2011
fDate
5-9 June 2011
Firstpage
339
Lastpage
344
Abstract
Ideally, multi-core instruction-set simulation should run in parallel to improve simulation performance. However, the conventional low-parallelism centralized scheduler greatly constrains simulation performance. To resolve this issue, we propose a high-parallelism distributed scheduling mechanism. The experimental results show that our proposed approach accelerates simulation by 6 to 20 times, depending on the number of cores.
Keywords
circuit simulation; instruction sets; logic design; microprocessor chips; multiprocessing systems; scheduling; high-parallelism distributed scheduling mechanism; low-parallelism centralized scheduler; multi-core instruction-set simulation; Clocks; Delay; Multicore processing; Parallel processing; Scheduling; Synchronization; Instruction-set simulator; Multi-core simulation; Parallel simulation; Timing synchronization;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference (DAC), 2011 48th ACM/EDAC/IEEE
Conference_Location
New York, NY
ISSN
0738-100x
Print_ISBN
978-1-4503-0636-2
Type
conf
Filename
5981954
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