Transaction based pre-to-post silicon validation

Intel´s move towards the SoC paradigm comes with a compelling requirement for shorter time-to-market. To address that, we need to make both pre and post silicon validation more efficient. In this paper we focus on post-si functional validation, which consumes an increasing share of the overall product development timeline. We present a coherent Pre-to-Post workflow that aims to improve productivity of post-si validation and debug by proper investment in design for debug / validation (DFx) and in test development during pre-si stages. In this workflow, a central transactions and events definition repository serves as the backbone across pre-Si and post-Si activities. The transaction spec guides DFx work in pre-Si as well as test suite preparation in order to make the post-Si validation work productive. Usage of micro-architectural events and transactions raises the level of abstraction, and can help in getting better productivy, manageability, reusability, and less error prone Post-Si validation work.