Title :
High effective-resolution built-in jitter characterization with quantization noise shaping
Author :
Yin, Leyi ; Kim, Yongtae ; Li, Peng
Author_Institution :
Dept. of ECE, Texas A&M Univ., College Station, TX, USA
Abstract :
A novel built-in jitter characterization architecture combining quantization noise shaping and a partial Vernier delay structure is proposed for high resolution jitter measurement. The effective resolution is optimized at the system level as well as the circuit level. Using 90nm CMOS technology, an area of 0.008mm2 is occupied. The power consumption is 1.85mW. An effective resolution of 1.5ps is achieved.
Keywords :
CMOS integrated circuits; delays; integrated circuit noise; jitter; CMOS technology; built-in jitter characterization; high-resolution jitter measurement; partial Vernier delay structure; power 1.85 mW; quantization noise shaping; size 90 nm; Delay; Inverters; Jitter; Noise; Noise shaping; Quantization; Built-in jitter characterization; Vernier delay line; gated ring oscillator; noise shaping;
Conference_Titel :
Design Automation Conference (DAC), 2011 48th ACM/EDAC/IEEE
Conference_Location :
New York, NY
Print_ISBN :
978-1-4503-0636-2
