DocumentCode
549642
Title
Full-chip TSV-to-TSV coupling analysis and optimization in 3D IC
Author
Liu, Chang ; Song, Taigon ; Cho, Jonghyun ; Kim, Joohee ; Kim, Joungho ; Lim, Sung Kyu
Author_Institution
Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA
fYear
2011
fDate
5-9 June 2011
Firstpage
783
Lastpage
788
Abstract
This paper studies TSV-to-TSV coupling in 3D ICs. A full-chip SI analysis flow is proposed based on the proposed coupling model. Analysis results show that TSVs cause significant coupling noise and timing problems despite that TSV count is much smaller compared with the gate count. Two approaches are proposed to alleviate TSV-to-TSV coupling, namely TSV shielding and buffer insertion. Analysis results show that both approaches are effective in reducing the TSV-caused-coupling and improving timing.
Keywords
integrated circuit modelling; integrated circuit noise; optimisation; three-dimensional integrated circuits; timing; 3D IC; TSV shielding; buffer insertion; coupling noise; full-chip TSV-to-TSV coupling analysis; optimization; timing problems; Couplings; Integrated circuit modeling; Noise; Silicon; Three dimensional displays; Through-silicon vias; Timing; 3D IC; TSV-to-TSV coupling;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference (DAC), 2011 48th ACM/EDAC/IEEE
Conference_Location
New York, NY
ISSN
0738-100x
Print_ISBN
978-1-4503-0636-2
Type
conf
Filename
5981999
Link To Document