DocumentCode
549649
Title
Robust partitioning for hardware-accelerated functional verification
Author
Moffitt, Michael D. ; Sustik, Mátyás A. ; Villarrubia, Paul G.
fYear
2011
fDate
5-9 June 2011
Firstpage
854
Lastpage
859
Abstract
We introduce a method of partitioning for massively-parallel hardware accelerated functional verification. Our approach augments classical hypergraph partitioning to model temporal dependencies that maximize parallelization within the instruction memories of the machine. Simulation depth is further reduced by optimizing path criticality and cut directionality. Our techniques are demonstrated on an industrial accelerator containing 262,144 parallel processors, and benchmarked across designs containing up to 200 million gates.
Keywords
formal verification; graph theory; parallel processing; classical hypergraph partitioning; cut directionality optimization; hardware-accelerated functional verification; industrial accelerator; partitioning method; path criticality optimization; temporal dependencies; Acceleration; Computer architecture; Concurrent computing; Delay; Hardware; Logic gates; Schedules; functional verification; hardware acceleration; optimization; partitioning; simulation;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference (DAC), 2011 48th ACM/EDAC/IEEE
Conference_Location
New York, NY
ISSN
0738-100x
Print_ISBN
978-1-4503-0636-2
Type
conf
Filename
5982006
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