A highly manufacturable integration technology of 20nm generation 64Gb multi-level NAND flash memory

Author

Lee, Keun Woo ; Choi, Se Kyoung ; Chung, Sung Jae ; Lee, Hye Lyoung ; Yi, Su Min ; Han, Byeong Il ; Lee, Byung In ; Lee, Dong Hwan ; Seo, Ji Hyun ; Park, Noh Yong ; Kim, Hae Soo ; Kim, Hyung Seok ; Youn, Tae Un ; Noh, Keum Hwan ; Lee, Min Kyu ; Lee, Ju Ye

Author_Institution

R&D Div., Hynix Semicond. Inc., Icheon, South Korea

fYear

2011

fDate

14-16 June 2011

Firstpage

70

Lastpage

71

Abstract

Multi-level NAND flash memories with a 20nm design rule have been successfully developed for the first time. A 20nm rule wordline (WL) and bitline (BL) direction have been realized by Spacer Patterning Technology (SPT) of ArF immersion lithography. Key integration technologies include WL airgap with separate gate etch process and optimized control gate (CG) poly deposition process. In addition, many physical and electrical challenges are successfully demonstrated to overcome scaling limit of 20nm technology.

Keywords

NAND circuits; flash memories; integrated circuit manufacture; bitline direction; design rule; gate etch process; highly manufacturable integration technology; immersion lithography; multilevel NAND flash memory; optimized control gate polydeposition process; rule wordline airgap; size 20 nm; spacer patterning technology; Capacitance; Charge measurement; Electric fields; Flash memory; Interference; Logic gates; Loss measurement;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology (VLSIT), 2011 Symposium on

Conference_Location

Honolulu, HI

ISSN

0743-1562

Print_ISBN

978-1-4244-9949-6

Type

conf

Filename

5984514