Extraction of 3-D trap position in NAND flash memory considering channel resistance of pass cells and bit-line interference

As scaling down in the flash memory cell, random telegraph noise (RTN) leads broaden threshold voltage distribution. Especially in NAND flash memory string, there is a cell position dependence of threshold voltage change (ΔV_th) due to the RTN. This indicates that the channel resistances of pass cells in a cell string are affecting to RTN characteristics of a selected cell. The extraction of a trap position along the channel width direction has never been tried until now. In this work, we extract the exact position and energy of a trap considering channel resistances of pass cells for the first time. Moreover, we extract the trap position along the width direction by using the interference between adjacent bit-lines (BLs).