RF and mixed-signal performances of a low cost 28nm low-power CMOS technology for wireless system-on-chip applications

Extending RF/MS-CMOS to 28nm low power Poly/SiON node for the next generation wireless system-on-chip (SoC) applications makes most economic sense because, beyond 28nm, costly HiK/MG, double-patterning for many critical layers, complex local interconnect, and/or multi-gate structures will be required for more Moore scaling. Competitive peak fT/Fmax of 349/265GHz for NMOS, 242/184GHz for PMOS, with excellent mixed-signal properties, e.g. NFmin, linearity, device matching, and 1/f noise, and quality passives are reported to meet the requirements of 4G cellular transceivers and next generation connectivity WLAN/Bluetooth/GPS etc. Effects associated with layout dependency, poly pitch/orientation, and DFM-related rules, are shown to degrade device fT by as much as ~10%, thus, require careful optimization. Good correlations between fT and DC-measured “gm” are observed; therefore, for quick impact assessment of DFM-related structures, one can rely on quick DC-measured gm to give first-order results.